In the present semiconductor fabrication process, semiconductor chips are frequently attached to other chips or other electronic structures. The attachment of the chip is frequently accomplished by one of two different techniques. The first is a wire bonding process in which each of a series of I/O bump terminal on a chip built on an aluminum bonding pad is sequentially bonded to the connecting pads on a substrate. The second technique is a flip chip attachment method in which all the I/O bumps on the semiconductor chip are first terminated with a solder material. A frequently used solder material is a 97% lead/3% tin high melting temperature solder alloy. The semiconductor chip is then flipped over and the solder bumps are aligned and reflowed in a reflow furnace to effect all the I/O connections with the bonding pads on the substrate. One advantage achieved by the flip chip process is its applicability to very high density CMOS circuits and its high reliability in the interconnects formed when compared to the wire bonding process. The latter technique also has limitations in the number of I/O interconnections that can be made in high performance devices. One of the disadvantages of the flip chip process is that the process was originally designed for a high temperature bonding process and thus the solder bump material chosen for mechanical and electrical reliability is a high melting temperature lead/tin solder. The high melting temperature solder can only be bonded by reflowing the solder at above 350.degree. C. and therefore, limiting the process of bonding to high temperature substrates such as ceramic and the like. Others have attempted to find solutions to overcome this problem, for instance, by using alternative solder alloys that have lower melting temperatures. Even though most of the lower melting temperature alloys do not meet the reliability requirement for high performance, high density circuits.
One solution proposed by others for performing a direct chip attach of a chip to a card with high melting temperature lead/tin solder bumps is to pre-deposit a low temperature solder on the card prior to the chip attach. Others have attempted the process of evaporating additional tin cap onto the high temperature solder bump. Both techniques introduce added costs and cards with more complex structure. For instance, the first technique requires that molten solder be injected through patterned openings in a mask so that they can be deposited at the desired pad locations on a substrate. The injection process is relatively complex which leads to a higher fabrication cost.
Still others have attempted electrochemically plating a low temperature solder onto the metal pads of a receiving substrate card or board. The high temperature solder bumps installed on a semiconductor chip are then joined to the low temperature solder on the substrate or the board. The drawback of the process is that the electrochemical process which applies the low temperature solder bumps on the pads of the substrate is a very complicated process which involves various steps of seeding, photo processing, plating, etc. It is difficult to control the uniformity of the solder bump thickness and to prevent bridging problems from occurring between the bumps. The electrochemical plating process is also a high cost process.
It is therefore an object of the present invention to provide a method of forming interconnects on a semiconductor chip that does not have the drawbacks and shortcomings of the conventional methods.
It is another object of the present invention to provide a method of forming interconnects on a semiconductor chip such that the chip can be joined to a second electronic device in a low temperature bonding process.
It is a further object of the present invention to provide a method of forming interconnects on an electronic device by building interconnects with at least two different materials wherein a lower melting temperature material covers a higher melting temperature material.
It is another further object of the present invention to provide a method of forming interconnects on an electronic device by first forming a bump with a high melting temperature solder and then capping the bump with a low melting temperature solder.
It is yet another object of the present invention to provide a method of forming interconnects on an electronic device by first forming a low melting temperature solder in a mold and then transferring the molded solder onto high melting temperature solder bumps built on a semiconductor chip.
It is still another object of the present invention to provide a method of forming interconnects on an electronic device wherein a low melting temperature lead/tin solder is first formed in a mold and then transferred onto a high melting temperature lead/tin solder built on a semiconductor chip.
It is still another further object of the present invention to provide an electronic structure that has interconnects built on the structure with at least two different materials wherein one material which has a lower melting temperature substantially covers the other material which has a higher melting temperature.